Due to the excellent CMOS process compatibility of HfZrO₂ and the increase in the k-value arising from the Morphotropic Phase Boundary (MPB) between the t- and o-phases, it is considered a strong candidate for future DRAM capacitors. However, as the HZO film becomes thinner, its crystallization temperature increases, leading to potential interfacial damage with the electrode and posing challenges for integration into BEOL processes. To address these issues, this study demonstrates MWA HZO with improved interfacial properties and characteristics by lowering the crystallization temperature of HZO by over 250°C through a combined microwave annealing process.
We present HZO film near the morphotropic phase boundary (MPB) with an EOT of 3.6 Å and a low leakage current density (Jleak @ 0.8 V) of 7.010-8 A/cm2 using a microwave annealing (MWA) system. This is the lowest EOT reported for HZO films, which meets the Jleak limit of DRAM without wake-up. Such performance improvement is facilitated by low-temperature (≤350°C) BEOL-compatible MWA. The MWA supplies the energy required for HZO crystallization in both thermal and microwave forms, offering three key benefits: (i) It drastically reduces thermal budget (TB), suppresses interfacial dead layer formation, and enhances endurance (ĸ~62 at 1012 cycles). (ii) It only affects the HZO film and not the TiN electrodes, making the dipoles inside HZO vibrate. This enables selective and volumetric annealing in high-aspect-ratio structures, such as DRAM cell capacitors. (iii) It lowers the activation barrier for HZO crystallization compared to typical rapid thermal annealing (RTA). We experimentally verified this by quantifying activation energy (Ea) using electrical measurements under various TBs, finding that the Ea was 0.67 eV/f.u. for MWA, and 0.85 eV/f.u. for RTA.
We present record-low equivalent oxide thickness (EOT) of 2.4 Å with a remarkable dielectric constant (ĸ) of 64 at 4.1nm-thick hafnium-based films with no wake-up characteristics. In comparison to conventional HZO films, our remarkable achievement stems from the high-quality crystalline structure with less oxygen vacancies formed by a low-damage process, as evidenced by high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) images and electron energy-loss spectroscopy (EELS) analysis. In addition, with high-pressure annealing (HPA), we were able to reduce the annealing temperature to 450°C leading to a decrease in leakage current (1.5 order). Further, increasing the measurement temperature from 298K to 389K results in the high-K from 66 to 70, which is the theoretical limit of the ĸ value of t-phase.
We provide a methodology for designing thermally stable hafnia ferroelectric (FE) materials to be taken into account while fabricating 3D memory devices. We reveal the underlying origins for the thermal instability of hafnia FE materials in terms of kinetics and material science. Furthermore, we suggest adopting dopants whose ionic radius is smaller than Hf in the FE matrix as a feasible option to demonstrate a thermally stable hafnia FE material. Using this approach, robust ferroelectricity is achieved even at a subsequent thermal budget. This work contributes to the commercialization of FE devices by filling the gap between the functionality of FE materials and their process applicability for 3D devices.
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[MIFIS FE NAND Device with Positive Feedback of Gate-injected Qit’ and Polarization]
We experimentally demonstrate a remarkable performance improvement, boosted by the interaction of charge trapping & ferroelectric (FE) switching effects in metal-band engineered gate interlayer (BE-G.IL)-FE-channel interlayer (Ch.IL)-Si (MIFIS) FeFET. The MIFIS with BE-G.IL (BE-MIFIS) facilitates the maximized ‘positive feedback’ of dual effects, leading to low operation voltage (VPGM/VERS: +17/-15 V), a wide memory window (MW: 10.5 V) and negligible disturb at a biased voltage of 9 V. This work proves that the hafnia FE can play as a key enabler in extending the technology development of 3D VNAND, which is currently approaching a state of stagnation.
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[Origin of Disturbance in FeFET & Potential of TiO2 as a Breakthrough for Disturb-free NAND Cell]
We reveal the origin of disturbance issues in ferroelectric FETs with a MIFIS stack. To achieve both low-voltage operation and disturbance immunity, we introduce a multi-functional TiO2 layer, positioned between the G.IL and FE layer. Under the same operation voltage which is below 15 V, MIFIS FeFET with TiO2 improves the MW by 35 % compared to the device without TiO2. Notably, the proposed device remains disturbance-free (∆Vth ~ 0 V) even after 104 cycles of 9 V disturbance stress. Using a model framework which reflects the hysteresis sub-loop of FE, we clarify that partial ∆P acts as the primary driver of disturbances. This study highlights the potential of MIFIS FeFET for future NVM applications by decoupling the trade-off between low-voltage operation and disturbance issues.
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[Low-Voltage Operational FRAM Cell Capacitors and Optimization of 1T-nC Arrays]
We provide a methodology for designing an anti-ferroelectric (AFE) based FRAM cell capacitor that operates at low voltage (≤ 1 V), while achieving superior high and steep polarization (P) switching characteristics (23.5 μC/cm2), considering BEOL compatibility. Furthermore, through experimental demonstration and modeling, we validate that the steep P switching, closely related to the domain size of the AFE material, is a key enabler for mitigating disturbance issues in 1T-nC FRAM arrays. Our model framework determines the optimal number of stacks for the 1T-nC FRAM architecture from the perspective of disturbance characteristics. This work highlights the potential of hafnia materials in embedded cache memory, bridging the gap between P functionality and reliability.
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[New Structure NAND Flash Memory for Wide Memory Window with Oxide Channel]
We focus on oxide-channel (Ox.Ch.) based ferroelectric NAND (FeNAND) devices, integrating advanced components such as source-tied covering metal (SCM) and control dielectric (C.DE) to enhance performance. Specifically, we have developed a FeNAND structure that improves erase (ERS) efficiency and read operation by addressing the channel depletion issue in Ox.Ch. devices. The grounded SCM accumulates holes during ERS, significantly increasing the electric field across the gate interlayer and ferroelectric (FE) layer, thereby boosting ERS efficiency. Additionally, during the read operation of the erased states, the C.DE helps distribute the read voltage more effectively, intensifying Vth,ERS, which results in a wide memory window. Moreover, the proposed structure is compatible with current 3D-NAND fabrication processes, offering comparable channel hole pitch and density, making it a promising solution for high-performance, scalable non-volatile memory applications.
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[Negative Feedback Loop of Retention Loss in MIFIS FeFET and New Approach with Anti-Ferroelectrics]
We demonstrate a novel ferroelectric FET configuration, designed to expand memory window (MW) and enhance retention via two approaches: (i) the introduction of a charge trap layer (CTL) and (ii) the adoption of anti-ferroelectric (AFE) material. The retention loss in MIFIS FeFET is due to the negative feedback loop, involving the de-trap of interface trap charge from gate (Qit’) and the loss of polarization (P), which mutually accelerates the further loss of the other. Our first approach, CTL on top of FE, provides additional trap sites with deep trap levels, introducing the favorable charge (QN) with high stability, thus enhancing both MW and retention. Moreover, by utilizing the high spontaneous polarization (PS) and low remanent polarization (Pr) nature of AFE, we further improved the retention by increasing the proportion of QN and decoupling the negative feedback loop.
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[Negative Capacitance (NC) NAND Flash Memory for Lower PGM Voltage without State Disturbance]
To overcome the drawbacks of flash memories, various high-performance flash memory approaches with a functional blocking layer (BL) have been proposed. To enhance the device performance of MLC flash memory and continued scaling, BLs with a higher k value are necessary. Recently, both HfO2-based ferroelectric (FE)/dielectric (DE) and antiferroelectric (AFE)/DE have been proposed as BLs. HfO2 (A)FE has almost the same band structure as HfO2 DE and the switching capacitance increases during polarization switching. However, the presence of remanent polarization (Pr) degrades the performance and reliability of flash memories. In addition, as the (A)FE/DE BL capacitance enhancement due to (A)FE polarization switching is inevitably smaller than that of the constituent DE layer, a BL with higher capacitance enhancement characteristics is required to further improve the memory devices. In this context, we utilized the concept of negative capacitance for blocking oxide of the conventional NAND flash memory. Capacitance boosting effect form NC leads to the lower operation voltage of NAND flash memory by improving the tunneling efficiency, increasing the power efficiency of the system.