To realize low-power / high-density in-memory computing, we propose an unprecedented negative capacitance-charge trap flash (NC-CTF) memory based in-memory computing architecture. To stabilized the NC effect, it is necessary to form a HfO2 based reversible single-domain ferroelectric (RSFE) layer. The RSFE is caused by a flexoelectric effect and a surface effect, which generate a large internal field and surface polarization pinning. As a consequence, a recoverable NC effect can be achieved without using a bipolar electric field. The application of an AND flash-like cell layout and source-follower/charge-sharing VMM operation to high-performance NC-CTF has successfully demonstrated energy-efficient and high-throughput in-memory computing.

We show nonvolatile XNOR synapses with high density and accuracy using a monolithically stacked complementary ferroelectric field-effect transistor (C-FeFET) composed of a p-type Si MFMIS-FeFET at the bottom and a 3D stackable n-type Al:IZTO MFS-FeTFT, achieving 60F2 per cell (2C-FeFET). For adjusting the threshold voltage and improving the switching speed (100 ns) of n-type ferroelectric TFT, we employed a dual-gate configuration and a unique operation scheme, making it comparable to those of Si-based FeFETs. We performed array-level simulation with a 512 × 512 subarray size and a 3-bit flash ADC, demonstrating that the image recognition accuracies using the MNIST and CIFAR-10 data sets were increased by 3.17 and 14.07%, respectively, in comparison to other nonvolatile XNOR synapses. In addition, we performed system-level analysis on a 512 × 512 XNOR C-FeFET, exhibiting an outstanding throughput of 717.37 GOPS and an energy efficiency of 196.7 TOPS/W. We expect that our approach would contribute to the high-density memory systems, logic-in-memory technology, and hardware implementation of neural networks.

FTJ based TCAM is an innovative memory technology that merges the high-speed search capabilities of TCAM with the non-volatile properties of ferroelectric tunnel junctions. By utilizing ferroelectric materials, it retains data without power and operates with low power consumption and fast switching speeds. FTJ TCAM offers high density and scalability, making it suitable for applications like networking equipment and security systems. Overall, FTJ TCAM represents a promising advancement for future high-performance memory solutions.

Ferroelectric tunnel junctions (FTJs) represent a cutting-edge domain within the field of material science and electronic engineering, bridging the gap between fundamental physics and cutting-edge applications in information technology. At their core, FTJs exploit the unique properties of ferroelectric materials to control tunneling current across a thin barrier, making them exceptionally suitable for a variety of next-generation electronic devices.
Ferroelectric materials possess spontaneous polarization that can be reversed by the application of an external electric field. This intrinsic characteristic is harnessed in FTJs, where the polarization state of the ferroelectric layer affects the tunneling barrier height and shape, thus modulating the tunneling current. The sensitivity of the tunneling current to the polarization state opens up avenues for non-volatile memory devices with high speed, low power consumption, and excellent scalability.
TCAM Applications
In the context of TCAM, FTJs offer a promising pathway to overcome the limitations of conventional semiconductor-based TCAMs, such as high power consumption and scalability issues. FTJs can be utilized to create high-density, energy-efficient TCAMs by leveraging their non-volatile polarization states to represent the ternary logic required in TCAMs (i.e., 0, 1, and X for "don't care"). This enables the development of memory devices that are not only faster and more power-efficient but also capable of storing more information per cell, a critical advantage in applications requiring high-speed data searching and networking.
PUF Applications
For security applications, FTJs are increasingly being explored for their potential in creating Physical Unclonable Functions (PUFs). The inherent variability in the ferroelectric polarization switching process can be utilized to generate unique, device-specific signatures or "fingerprints." These fingerprints are extremely challenging to replicate or predict, making FTJs an excellent candidate for hardware-based security tokens and anti-counterfeiting measures. In PUF applications, the stochastic nature of the ferroelectric domain structure in FTJs ensures that each device is inherently unique, providing a robust foundation for secure communications, authentication, and data protection.

The MFMIS-based Leaky charge trap flash can be used as a neuromorphic device by utilizing the trap and charge loss phenomena of gate-injected charges under applied voltage. To induce spontaneous charge loss, it is necessary to intentionally degrade the retention characteristics of the device. Therefore, an additional annealing method to form Leaky HZO is required. As leaky Anti-ferroelectric (AFe) has a Pr value of approximately 0 at no applied electric field, its retention time is more than 50 times shorter compared to leaky ferroelectric (Fe). This enables self-refresh capabilities, making it suitable for application in high-speed and low-voltage neuromorphic devices. In this regard, we are currently employing AFeCTF device for neuromorphic computing. We can adjust CDE;CFE ratio in the device fabrication level, which is named 3D AFeCTF. In the case of reservoir computing (RC), we applied AFeCTF as a physical reservoir computing device with its short-term memory characteristics. We can obtain more reservoir states with varying decay time of the device. The main application for the RC with AFeCTF is data encoding based in-sensor processing. In the case of spiking neural network (SNN), we applied AFeCTF as a leaky-integration and fire device with is spontaneous leaky and charge ingetration behavior. Integration with additional CMOS circuits for implementing the LIF model shows promising potential for use in SNN processing units.

To address the bottleneck problem of the von Neumann architecture, Process in Memory (PIM), which performs certain operations directly within the memory, has been proposed. However, PIM implementations using Non-volatile memory (NVM) technologies such as NOR flash, PCM, STT-MRAM, and ReRAM face several limitations, including reliability issues. Additionally, CMOS-based synapse devices have challenges such as cell leakage and non-linearity. By utilizing Oxide Channel TFT, we can effectively resolve the cell leakage problem and achieve high retention, which is crucial for reliable weight storage.
To ensure linear PIM characteristics, increasing the capacitance value is essential. Therefore, we introduce a supercapacitor that leverages the capacitance boosting effect based on the negative capacitance phenomenon. This not only enhances computational accuracy by achieving high capacitance within a small area, but also reduces the overall footprint. Through SPICE modeling, our research team has confirmed improvements in sensing margin and linearity when employing supercapacitors.