Processing in memory is a next-generation computing architecture beyond the conventional von Neumann computing architecture, and FeFET has been widely studied as a promising computational memory device based on their fast operation speed, high reliability and CMOS compatibility. Our group is actively conducting various research to develop an optimal FeFET for performing multiply and accumulation (MAC) operations, which is the most primary calculations in machine learning. In detail, we are introducing key approaches covering material and device architecture to overcome current technological issues. Moreover, using various computing logic, we are demonstrating the FeFET-PIM array with a high energy efficiency, which is evaluated by the system-level simulation.

Modern computing technologies require significant computing power, huge storage capacity, and an expanded communication bandwidth owing to extensive applications that use huge amounts of data, such as machine learning and edge computing. To achieve high efficiency in power-delay-area parameters, considerable efforts have been made to optimize both the processor and the memory capacity. Non-Volatile Logic-in-Memory (NV-LiM) has been proposed to prevent performance degradation due to intra-chip global wires, by locating non-volatile memory in logic and eliminating standby power consumption during power-gating. Among them, unlike other NV memory devices, the hafnia-based FeFET shows three-terminal amplifying characteristics and selector functionality, demonstrating a high Ion/Ioff ratio and implementing CMOS logic without requiring additional switch devices.

We demonstrate the novel approach to superior multi-level-cell FeFET with a large memory window (MW) and negligible VT variation toward quadruple-level-cell (QLC) operation. We realized high ferroelectricity in a relatively thick HZO ferroelectric (FE) layer for FeFET with a large MW (MW ∝ thickness of FE layer (TFE)) based on our understanding of thermodynamics and kinetics. Moreover, we employed the MFMIS gate stack having a floating gate for FeFET to minimize the VT variation with respect to different distributions of phase & grain size. We applied experimentally obtained materials and electrical data of HZO to TCAD simulation to statistically analyze the impact of materials and gate stack on the MW and the VT variation of FeFET.

To overcome the drawbacks of flash memories, various high-performance flash memory approaches with a functional blocking layer (BL) have been proposed.
To enhance the device performance of MLC flash memory and continued scaling, BLs with a higher k value are necessary. Recently, both HfO2-based ferroelectric (FE)/dielectric (DE) and antiferroelectric (AFE)/DE have been proposed as BLs. HfO2 (A)FE has almost the same band structure as HfO2 DE and the switching capacitance increases during polarization switching. However, the presence of remanent polarization (Pr) degrades the performance and reliability of flash memories. In addition, as the (A)FE/DE BL capacitance enhancement due to (A)FE polarization switching is inevitably smaller than that of the constituent DE layer, a BL with higher capacitance enhancement characteristics is required to further improve the memory devices. In this context, we utilized the concept of negative capacitance for blocking oxide of the conventional NAND flash memory. Capacitance boosting effect form NC leads to the lower operation voltage of NAND flash memory by improving the tunneling efficiency, increasing the power efficiency of the system.

To realize low-power / high-density in-memory computing, we propose an unprecedented negative capacitance-charge trap flash (NC-CTF) memory based in-memory computing architecture. To stabilize the NC effect, it is necessary to form a HfO2 based reversible single-domain ferroelectric (RSFE) layer. The RSFE is caused by a flexoelectric effect and a surface effect, which generate a large internal field and surface polarization pinning. As a consequence, a recoverable NC effect can be achieved without using a bipolar electric field. The application of an AND flash-like cell layout and source-follower/charge-sharing VMM operation to high-performance NC-CTF has successfully demonstrated energy-efficient and high-throughput in-memory computing.

Ferroelectric tunnel junctions (FTJs) represent a cutting-edge domain within the field of material science and electronic engineering, bridging the gap between fundamental physics and cutting-edge applications in information technology. At their core, FTJs exploit the unique properties of ferroelectric materials to control tunneling current across a thin barrier, making them exceptionally suitable for a variety of next-generation electronic devices.
Ferroelectric materials possess spontaneous polarization that can be reversed by the application of an external electric field. This intrinsic characteristic is harnessed in FTJs, where the polarization state of the ferroelectric layer affects the tunneling barrier height and shape, thus modulating the tunneling current. The sensitivity of the tunneling current to the polarization state opens up avenues for non-volatile memory devices with high speed, low power consumption, and excellent scalability.
TCAM Applications
In the context of TCAM, FTJs offer a promising pathway to overcome the limitations of conventional semiconductor-based TCAMs, such as high power consumption and scalability issues. FTJs can be utilized to create high-density, energy-efficient TCAMs by leveraging their non-volatile polarization states to represent the ternary logic required in TCAMs (i.e., 0, 1, and X for "don't care"). This enables the development of memory devices that are not only faster and more power-efficient but also capable of storing more information per cell, a critical advantage in applications requiring high-speed data searching and networking.
PUF Applications
For security applications, FTJs are increasingly being explored for their potential in creating Physical Unclonable Functions (PUFs). The inherent variability in the ferroelectric polarization switching process can be utilized to generate unique, device-specific signatures or "fingerprints." These fingerprints are extremely challenging to replicate or predict, making FTJs an excellent candidate for hardware-based security tokens and anti-counterfeiting measures. In PUF applications, the stochastic nature of the ferroelectric domain structure in FTJs ensures that each device is inherently unique, providing a robust foundation for secure communications, authentication, and data protection.